1. Field of the Invention
The present invention relates to a circuit and method for protecting semiconductor integrated circuits. More particularly, the present invention relates to a circuit and a method for electrostatic discharge (ESD) protection within semiconductor integrated circuits.
2. Description of the Related Art
Because of high level integration of semiconductor integrated circuits, product reliabilities are more and more important for the circuits. One concern to the integrated circuits is the vulnerability to electrostatic damage (ESD). An ESD pulse occurs once the pins or input/output bond pads of the integrated circuits are charged with a high voltage or current resulting from a body or material that is statically charged. Usually the voltage charged is more than 100V and in a short period time about 10 to several hundred nanoseconds (ns). Due to the sharp but short voltage or current pulse, the internal devices of the integrated circuits cannot withstand the abnormal voltage drop and are frequently destroyed. Therefore, ESD protection circuits are designed and connected to input/output (I/O) pads and internal integrated circuits to provide an additional current path for bypassing the voltage or current pulse.
FIG. 1 illustrates a prior art ESD protection circuit. An I/O pad 100 is connected to an ESD protection circuit. The ESD protection circuit includes a P-type metal-oxide-semiconductor (PMOS) transistor 150 and a stacked NMOS (ST NMOS) transistor 110. The ST NMOS has been proposed and used for tolerating an ESD pulse in mixed-voltage I/O circuits. The ST NMOS transistor 110 includes a first NMOS transistor 130 and a second NMOS transistor. The gate terminal of the first NMOS transistor 130 is coupled to a Vcc terminal, and the gate terminal of the second NMOS transistor 140 is coupled to an output of a NMOS pre-driver circuit 160. The source terminal of the second NMOS transistor 140 is coupled to a Vss terminal. The PMOS 150 has a gate terminal coupled to a PMOS pre-driver circuit 120, and a source terminal coupled to the Vcc terminal. When a positive ESD pulse is applied to the I/O pad 100, the first NMOS transistor 130 and the second NMOS transistor 140 turn on and create an additional current path whereby the current is conducted to the Vss terminal. If a negative ESD pulse is charged to the I/O pad 100, the PMOS 150 will turn on and create an additional path conducting the current from the Vcc.
However, in positive ESDIVss zapping event, the ESD protection circuit shown in FIG. 1 is more vulnerable to an ESD pulse. The vulnerability of the ESD protection circuit results from the fact that a current crowds at the channel region of the first NMOS 130, so as to disturb the performance of the ESD protection circuit. This phenomenon is called gate voltage-induced current crowding (GVICC) effects.
Therefore, it is desirable to provide a circuit or a method for ESD protection which eliminates or substantially reduces the GVICC effects.